A Dithered Carrier Level Shifted Sine Pulse Width Modulation Technique for EMI Reduction in Cascaded H-Bridge Multi-Level Inverters

Abstract

Growing utilization of high-power equipment, particularly in renewable energy systems and electric vehicle applications, has increased the popularity of multi-level inverters (MLI), owing to their capacity to produce high-fidelity sine wave output, compactness, and readily modifiable control devices. Electromagnetic Interference (EMI) is a prevalent problem associated with MLI topologies. Passive EMI filters can easily eliminate this problem. Still, the bulky components used inside these filters lead to a rise in the system's overall size, weight, and production cost. This work presents a novel modulation technique called dithered carrier level shifted sine pulse width modulation (DCLS-SPWM) with the target of reducing electromagnetic interference in cascaded H-bridge multi-level inverters (CHB-MLIs). This method reduces EMI by diffusing harmonics, typically concentrated in lower frequency bands, into higher stages. In the case of DCLS-SPWM, the carrier signal frequency is dithered over a time interval while maintaining the same overall number of switching events. This destabilizes the steady-state conditions intrinsic to the modulation, resulting in a more uniform harmonic distribution. In this study, a 9-level CHB-MLI simulation is built using MATLAB-Simulink, where each module receives a 100V DC input. The efficacy of the proposed DCLS-SPWM method on harmonic reduction is analyzed and validated.